“"We actually made it on breadboards, since it was hardwired the bread-board is now a sea of wires everywhere, and some things are not working too. I am thinking of getting a custom PCB just for the control unit to make it presentable." — CorRupT9 (https://news.ycombinator.com/it...”
You know that feeling when a computer architecture textbook shows you a CPU control unit as a box labeled 'microcode ROM' and you nod along — but you have no intuition for which gate actually switches on when the CPU needs to load a register? Microcode hides that mapping in a ROM you cannot open. STEPLA-1 replaces that ROM with explicit AND/OR gate combinations, so every control signal has a visible, traceable physical cause. The cost is that the breadboard build is now, in the creator's own words, 'a sea of wires everywhere, and some things are not working too.'
STEPLA-1 fetches an 8-bit instruction from Instruction SRAM. The top 4 bits select one of 16 operations; the bottom 4 bits encode source and destination registers (RA–RD). Instead of looking up required control signals in an EEPROM, the control unit drives each control wire from a combination of AND/OR gates keyed directly to the current opcode bits — a PLA-inspired gate matrix. The clock runs in two phases: the control logic evaluates on the first phase, the data path acts on the second, giving the gates time to settle before any flip-flops latch. A Bootstrap Control Unit runs once on power-on, copying a ROM image into Instruction SRAM, then hands control to the main CPU.
If you are an EE or CS undergraduate studying computer organization, or an engineer who wants to trace every control signal in a CPU down to the gate level with full documentation, this is a rare reference design. Also useful for instructors looking for a concrete, open-source teaching artifact. Not useful if you need a production CPU, want interrupt support, or plan to synthesize directly to an FPGA without reworking the non-standard dual-phase clock.
Worth reading the spec document and stepping through the Logisim simulation if you are studying computer architecture at the gate level — the hardwired control unit is a genuinely uncommon reference design with unusually thorough documentation for a student project. Not a platform to build on: no interrupt support, the physical build has unresolved wiring issues, no versioned releases, and extending the ISA requires redesigning the gate matrix rather than updating a ROM.
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